Cruz's Honours Projects for 2009

This page contains a brief description of the projects I am willing to supervise this year. If you are interested in any of the below projects, come and I will explain more about it.

Any other proposals in the area of interconnection networks are welcome.

A few words about my research

My main area of expertise is interconnection networks for Parallel Computers. My main goal is to design fast networks that support the traffic produced by the parallel nodes in the most efficient way. Thus, my works spreads into other areas such as traffic characterization of parallel benchmarks, distributed memory systems that rely on cache coherent protocols (also called cc-NUMA architectures) and mapping of tasks.
Most of the research is carried out using network simulators. In particular, I have used a simple C simulator called chaosSim and a very powerful C++ simulator called Sycosis. This latter one has been integrated into a Parallel system simulator called RSim which emulates a parallel system. Thus, we can "execute" parallel applications such such as the SPLASH-2 suite and the impact that the network will have on their execution time.

Another area of interest is routing in ad-hoc mobile network

The Projects

Routing strategies for Networks on Chip (NoC)

This project explores the design of worhmole routers for a Network on chip (NoC).

Background

In 2006, Intel released the first processor to contain more than one billion transistors, and in Feruary 2008 Intel presented its quad-core Itanium, the first processor to exceed two billion transistors, at the International Solid-State Circuits Conference (ISSCC). The design of billion-transistor semiconductor chips faces demanding challenges due to huge complexity of systems and increasing design productivity gap. Network on chip (NOC) is new architecture template that helps to deal with the design of such system. Project Domain A NoC template divides the chip into contigous areas called regions which are physically isolated from each other but have special mechanism for communication among each other. A region of NoC will be composed of computing resources in the form of processor cores and field programmable logic blocks, distributed storage resources, programmable I/O etc. All these resources interconnected by a switching fabric, allowing any resource to communicate with any other resource. In other words a small network system replaces the system bus, in order to allow multiple resources to communicate at the same time. NoCs can borrow concepts and techniques from traditional networks, but it will be impractical to just reuse features of classical computer networks. In particular, routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Although NoC paradigm does not dictate the topology, the regularity of topology is considered as a requirement and most of the work focuses on 2D regular topologies with a low number of nodes such a 3x3 mesh.

Goal

The goal of this project is to a comparative analysis of the routing strategies for NoC suggested in the literature with emphasis on understanding the traffic demands of the system and the limitations of each routing strategy.

Plan

Most of the routing strategies for NoC are extension of worhmole routing for 2D meshes, this the first step is to review and compare the adaptive router proposals of NoC with previous 2D interconnection network design which were also resource limited. After this review phase, network simulation will be used to evaluate performance of the best three NoC proposals under a range on synthetic patterns. You will need to have good skills at C/C++ programming and basic system management knowledge, in order to install, test and use a range of network simulator tools.

Modelling reactive traffic for Networks on Chip (NoC)

The goal of this project is to extend synthetic traffic simulation with synthetic tasks than interact with each other via messages. The literature review should identify a list of benchmarks programs which should be analyzed both statically and dynamically in order to determine the kind of traffic that must be supported by the NoC.