Bibliography

This is a growing list of papers (97) I have read (or am in the process of reading or re-reading!) and will be updated on a regular basis. I've tried to classify them into the listed categories. The number of references in each category is in parentheses and italicised at the end of each link. At the end of each reference the Biblink is used by me to manage the references.
  1. Sources on VHDL and other HDLs
    1. Peter J. Ashenden, The Designer's Guide to VHDL, Morgan Kauffman, San Francisco, 1996. Biblink
    2. P. J. Ashenden and P. A. Wilsey, "Considerations on Object-Oriented Extensions to VHDL," Proceedings of VHDL International Users Forum Spring-97 Conference, Santa Clara, California (April 1997), pp. 109-118. Biblink
    3. P. J. Ashenden and P. A. Wilsey, "Extensions to VHDL for Abstraction of Concurrency and Communication," Proceedings of Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS '98), Montreal, Canada (July 1998), pp. 301-308. Biblink
    4. P. J. Ashenden, Robert Esser and P. A. Wilsey, "Communication and Synchronization Using Bounded Channels in SUAVE," Proceedings of International Hardware Description Languages Conference, HDLCON '99 , Santa Clara, California (April 1999), to appear. Biblink
    5. P. J. Ashenden and P. A. Wilsey, "A Comparison of Alternative Extensions for Data Modeling in VHDL," Proceedings of Hawai'i International Conference on System Sciences, Kona, Hawaii (January 1998). Biblink
    6. P. J. Ashenden and P. A. Wilsey, "Considerations on System-Level Behavioural and Structural Modeling Extensions to VHDL," Proceedings of VHDL International Users Forum Spring-98 Conference, Santa Clara, California (March 1998), pp. 42-50. Biblink
    7. P. J. Ashenden, P. A. Wilsey and D. E. Martin, "SUAVE: Extending VHDL to Improve Modeling Support," IEEE Design and Test of Computers (April-June 1998), pp. 34-44. Biblink
    8. P. J. Ashenden, P. A. Wilsey and D. E. Martin, "SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling," Proceedings of Forum on Design Languages (FDL '98), Vol. 1, Lausanne, Switzerland (September 1998), pp. 93-102. Biblink
    9. P. J. Ashenden and P. A. Wilsey, "Principles for Extensions to VHDL for High-Level Modeling," VLSI Design (1999), to appear. Biblink
    10. P. J. Ashenden and P. A. Wilsey, "Protected Shared Variables in VHDL: IEEE Std 1076a," IEEE Design and Test of Computers (1999), to appear. Biblink
    11. P. J. Ashenden and P. A. Wilsey and Dale E. Martin, "Reuse Through Genericity in SUAVE," Proceedings of VHDL International Users Forum Fall-97 Conference, Arlington, VA (October 1997), pp. 170-177. Biblink
    12. P. J. Ashenden and P. A. Wilsey and Dale E. Martin, "SUAVE: Painless Extension for an Object-Oriented VHDL," Proceedings of VHDL International Users Forum Fall-97 Conference, Arlington, VA (October 1997), pp. 60-67. Biblink
    13. Jayaram Bhasker, A VHDL Primer, Prentice Hall Series in Innovative Technology, Englewood Cliffs, 1992. Biblink
    14. Ben Cohen, VHDL: Answers to Frequently Asked Questions, Kluwer Academic Publishers, Boston, 1997. Biblink
    15. Yatin V. Hoskote, Jacob A. Abraham, Donald S. Fussell and John Moondanos, "Automatic verification of implementations of large circuits against HDL specifications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 3, March, 1997, pp. 217 - 228.
      16. Biblink
    16. K. E. Kerry, P. J. Ashenden and M. J. Oudshoorn, "STEVE: A Syntax-Directed Editor for VHDL Based on SAVANT," Proceedings of VHDL International Users Forum Spring-97 Conference, Santa Clara, California (April 1997), pp. 71-78. Biblink
    17. Kwang Il Park and Kyu Ho Park, "Suppression by optimizing VHDL programs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 no. 8, August, 1998, pp. 662 - 691.
      18. Biblink
    18. Frits D. Schalij, Tangram Manual, Nat. Lab. Technical Note Nr. UR 008/93, Philips Electronics, 1996. Biblink
    19. John Sanguinetti, "Hardware Description Languages", http://www.vol.webnexus.com/Sample/overview/hdl.html, 1996, [online 21st February, 1999]. Biblink
    20. Verilog FAQ, http://www.angelfire.com/in/verilogfaq/page2.html, [online 21st February, 1999]. Biblink
    21. Peter A. Walker and Sumit Ghosh, "On the nature and inadequacies of transport timing delay constructs in VHDL descriptions", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 8, August, 1997, pp. 894 - 915.
      22. Biblink
  2. Sources primarily on design and some fundamental background
    1. Daniel D. Gajski, Principles of Digital Design, Prentice Hall, New Jersey, 1997. Biblink
    2. Catherine H. Gebotys and Mohamed I. Elmasry, Optimal VLSI Architectural Synthesis: Area, Performance and Testability, Kluwer Academic Publishers, London, 1992. Biblink
    3. C.A.R. Hoare, "Communicating Sequential Processes", Communications of the ACM, Vol. 21, No. 8, August, 1978, pp. 666 - 677. Biblink
    4. C.A.R. Hoare, Communicating Sequential Processes, Prentice-Hall International Series in Computer Science, Englewood Cliffs, 1985. Biblink
    5. Timothy Kam, Tiziano Villa, Robert K. Brayton and Alberto L Sangionvanni-Vincentelli, "Implicit computation of compatible sets for state minimization of ISFSM's", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 7, July, 1997, pp. 657 - 676. Biblink
    6. Ivan E. Sutherland, "Micropipelines", Communications of the ACM, vol. 32 no. 6, pp. 720 - 738, June 1989. Biblink
    7. Filip Thoen, Jan Van Der Steen, Gjalt de Jong, Gert Goossens and Hugo De Man, "Multi-thread graph: a system model for real-time embeded software synthesis", Proceedings of the European Design and Test Conference, 1997, pp. 476 - 581
      8. Biblink
    8. Frank Vahid, "Procedure cloning: A transformation for improved system-level functional partitioning", Proceedings of the European Design and Test Conference, 1997, pp. 487 - 492.
      9. Biblink
  3. Sources with strong usage of CDFGs or extremely useful to research on CDFGs
    1. E. Berrebi, P. Kission, S. Vernalde, S. De Troch, J.C. Herluison, J. Frehel, A.A. Jerraya and I. Bolsens, "Combined control flow dominated and data flow dominated high-level synthesis", Proceedings of the 33rd Design Automation Conference, 1996, pp 573 - 578.
      2. Biblink
    2. Douglas M. Blough, Fadi J. Kurdahi and Seong Y. Ohm, "Optimal algorithms for recovery point insertion in recoverable microarchitectures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 9, September, 1997, pp 945 - 955.
      3. Biblink
    3. Claudionor Nunes Coelho Jr. and Giovanni De Micheli, "Analysis and synthesis of concurrent digital circuits using control-flow expressions", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15 no. 8, August, 1996, pp 854 - 876.
      4. Biblink
    4. M. Colli and P. Palazzari, "Real time pipelined system design through simulated annealing", Journal of Systems Architecture, vol. 42, 1996, pp 465 - 475.
      5. Biblink
    5. Aurobindo Dasgupta and Ramesh Karri, "Electromigration reliability enhancement via bus activity distribution", Proceedings of the 33rd Design Automation Conference, 1996, pp 353 - 356.
      6. Biblink
    6. Phil Endecott, "SCALP: A Superscalar Asynchronous Low-Power Processor", URL: http://maveric0.uwaterloo.ca/amulet/staff/details/phil/scalp/, 19th March, 1999.
      7. Biblink
    7. Indradeep Ghosh and Niraj K. Jha, "High-level test synthesis: a survey", Integration: the VLSI journal, vol 26, 1998, pp 79 - 99. Biblink
    8. Sriram Govindarajan, Naren Narasimhan and Ranga Vemurri, "Dependency analysis and operation graph generation for high-level synthesis from behavioral VHDL", http://www.ececs.uc.edu/~ddel/projects/dss/dss.html, 1st April, 1999.
      9. Biblink
    9. T. Grötker, R. Schoenen and H. Meyr, "PCC: A modeling techquique for mixed control/data flow systems", Proceedings of the European Design and Test Conference, 1997,pp 482 - 486.
      10. Biblink
    10. Shih-Hsu Huang, Yu-Chin Hsu and Yen-Jen Oyang, "A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits", Microprocessing and microprogramming, vol 41, 1995, pp 501 - 519.
      11. Biblink
    11. Balakrishnan Iyer and Ramesh Karri, "Introspection: A low overhead binding technique during self-diagnising microarchitecture synthesis", Proceedings of the 33rd Design Automation Conference, 1996, pp 137 - 142.
      12. Biblink
    12. Ganesh Lakshminarayana, Kamal S. Khouri and Niraj K. Jha, " Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions ", IEEE/ACM International Conference on Computer-Aided Design, 1997, pp.244-250.
      13. Biblink
    13. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha and Sujit Dey, "Power management in High-Level Synthesis", IEEE Transactions on Very Large Scale Integration Systems, vol. 7, no. 1, March. 1999, pp 7 - 15.
      14. Biblink
    14. Naren Narasimhan and Ranga Vemurri, "Specification of control flow properties for verification of synthesized VHDL designs", URL http://www.ececs.uc.edu/~ddel/projects/dss/dss.html, 1st April, 1999.
      15. Biblink
    15. John A. Nestor and Ganesh Krishnamoorthy, "SALSA - A new approach to scheduling with timing constraints", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 12 no. 8, August 1993, pp. 1107-1122.
      16. Biblink
    16. Ishwar Parulkar, Sandeep K. Gupta and Melvin A. Breuer, "Lower bounds on test resources for scheduled data flow graphs", Proceedings of the 33rd Design Automation Conference, 1996, pp 143 - 148.
      17. Biblink
    17. Miodrag Potkonjak, Sujit Dey and Rabindra K. Roy, "Behavioral synthesis of area-efficient testable designs uing interaction between hardware sharing and partial scan ", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 14, No 9, September, 1995, pp 1141 - 1154.
      18. Biblink
    18. Anand Raghunathan and Niraj K. Jha, "SCALP: An iterative-improvement-based low-power data path synthesis system", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 11, November, 1997, pp 1260 - 1277.
      19. Biblink
  4. Sources primarily on High Level Synthesis
    1. Mohammed Aloqeely and C. Y. Roger Chen, "Sequencer-based data path synthesis of regular iterative algorithms", Proceedings of the European Design Automation Conference, 1994, pp. 155 - 160.
      2. Biblink
    2. Christian Blumenröhr, Dirk Eisenbiegler and Detlef Schmod, "On the efficiency of formal synthesis - experimental results", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18 no. 1, January, 1999, pp. 25 - 32.
      3. Biblink
    3. Jens P. Brage, Foundations of a High-Level Synthesis system, PhD Thesis, Center for Integrated Electronics, Dept. of Computer Science, Technical University of Denmark, TR 1993-121, 1994. Biblink
    4. Oliver Bringmann and Wolfgang Rosenstiel, "Resource sharing in hierarchical synthesis", Proceedings of the IEEE/ACM International Conference on CAD-97, 1997, pp. 318 - 325.
      5. Biblink
    5. Raul Camposano, "Behavioral synthesis", Proceedings of the 33rd Design Automation Conference, Las Vegas, 1996, pp 33 - 34. Biblink
    6. Ajay J. Daga and William P. Birmingham, "Interface finite-state machines: definition, minimization, and decomposition", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 5, May, 1997, pp. 497 - 505.
      7. Biblink
    7. Yung-Ming Fang and D. F. Wong, "Simultaneous functional-unit binding and floorplanning", Proceedings of the IEEE/ACM International Conference on CAD-94, 1994, pp. 317 - 321.
      8. Biblink
    8. Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid and Peter Fung,"System design methodologies: Aiming at the 100 h design cycle", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4 no. 1, March, 1996, pp. 70 - 82.
      9. Biblink
    9. Daniel D. Gajski and Loganath Ramachandran, "Introduction to High-Level Synthesis", IEEE Design and Test of Computers, Winter, 1994, pp 44 - 54 Biblink
    10. Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang,"PSM: An object-oriented synthesis approach to multiprocessor system design", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4 no. 1, March, 1996, pp. 83 - 97.
      11. Biblink
    11. Youn-Long Lin, "Survey Paper: Recent developments in high-level synthesis", ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 1, January, 1997, pp 2 - 21. Biblink
    12. Seong Yong Ohm, Fadi J. Kurdahi and Nikil D. Dutt, "A unified lower bound estimation technique for high-level synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 5, May, 1997, pp. 458 - 472.
      13. Biblink
    13. Anand Raghunathan and Niraj K. Jha, "SCALP: An iterative-improvement-based low-power data path synthesis system", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 11, November, 1997, pp. 1260 - 1261.
      14. Biblink
    14. Kenneth D. Wagner and Dey Sujit, "High-Level Synthesis for testability: A survey and perspective", Proceedings of the 33rd Design Automation Conference, Las Vegas, 1996, pp 131 - 136. Biblink
  5. Sources primarily on Asynchronous and Concurrent System Design
    1. Background
      1. Janusz A. Brzozowski and Carl-Johan H. Seger, Asynchronous circuits, Springer-Verlag, New York, 1994. Biblink
    2. Specific applications
      1. Andrew Bailey and Mark B. Josephs, "Sequencer circuits for VLSI programming", Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, May 1995, pp 82 - 90. Biblink
      2. Kees van Berkel, Ronan Burgess, Joep Kessels, Marly Roncken, Frits Schalij and Ad Peeters, "Asynchronous circuits for low power: A DCC error corrector", IEEE Design and Test of Computers, Summer, 1994, pp 22 - 32. Biblink
      3. Wolfgang Budde, Hans-Georg Keller, Hans-Jürgen Reumerman and Paul van der Wiel, "An asynchronous, high-speed packet switching component", IEEE Design and Test of Computers, Summer, 1994, pp 33 42. Biblink
      4. Joep Kessels, "VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player", Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, May 1995, pp 44 - 52. Biblink
      5. D. J. Kinniment,"An evaluation of asynchronous addition", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4 no. 1, March, 1996, pp. 137 - 140.
        6. Biblink
      6. Alan Marshall, Bill Coates and Polly Siegel, "Designing an asynchronous communications chip", IEEE Design and Test of Computers, Summer, 1994, pp 8 - 21. Biblink
      7. Charles E. Molnar, Ting-Pien Fang and Frederick U. Rosenberger, Synthesis of Delay-Insensitive Modules, Technical Memorandum No. 307, Institute for Biomedical Computing, Washington University, St. Louis, Missouri, March,1985. Biblink
      8. Takashi Nanya, Yoichiro Veno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura, "TITAC: Design of a quasi-delay-insensitive microprocessor", IEEE Design and Test of Computers, Summer, 1994, pp 50 -63. Biblink
      9. Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, Frits Schalij and Rik van Wiel, "A single-rail re-implementation of a DCC error detector using a generic standard-cell library", Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, May 1995, pp 72 - 79. Biblink
    3. Synthesis methods for Asynchronous Circuits and mixed mode circuits
      1. Peter A. Beerel, Chris J. Myers and Teresa H. Meng, "Covering conditions and algorithms for the synthesis of speed-independent circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 no. 3, March, 1998, pp. 205 - 219.
        2. Biblink
      2. Srimat T. Chakrahuar, Savita Banerjee, Rabindra K. Roy and Dhiraj K. Pradhan, "Synthesis of initializable asynchronous circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4 no. 5, June, 1996, pp.254 - 263.
        3. Biblink
      3. Tam-Anh Chu, Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications, PhD Thesis, Department of Electrical Engineering and Computer Science, MIT, May, 1987. Biblink
      4. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno and Alexandre Yakovlev, "A region-based theory for state assignment in speed-independent circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 8, August, 1997, pp. 793 - 812.
        5. Biblink
      5. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno and Alex Yakovlev, "Methodology and tools for state encoding in asynchronous circuit synthesis", Proceedings of the 33rd Design Automation Conference, Las Vegas, 1996, pp 63 - 66. Biblink
      6. C. Farnsworth, D. A. Edwards, Jian Wei Lui and S. S. Sikand, "A hybrid asynchronous system design environment", Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, May 1995, pp 91 - 98. Biblink
      7. Scott Hauck, "Asynchronous Design Methodologies: An Overview", Proceedings of the IEEE, Vol. 83, No. 1, January, 1995, pp 69 - 93. Biblink
      8. John O'Leary and Geoffrey Brown, "Synchronous emulation of asynchronous circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 2, February, 1997, pp. 205 - 209.
        9. Biblink
      9. A. Semenov, A. Yakovlev, E. Pastor, M. A. Peña and J. Cortadella, "Synthesis of speed-independent circuits from STF-unfolding segment", Proceedings of the Design Automation Conference, 1997, pp. 16 - 21.
        10. Biblink
      10. Jurgen Teich, Lothar Thiele, Sundararajan Sriram and Michael Martin, "Performance analysis and optimization of mixed asynchronous synchronous systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 5, May, 1997, pp. 473 - 484. Biblink
      11. Kenneth Y. Yun and David L. Dill, "Automatic synthesis of extended burst-mode circuits Part 1 (Specification and hazard-free implementations)", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18 no. 2, February, 1999, pp. 101 - 117.
        12. Biblink
      12. Kenneth Y. Yun and David L. Dill, "Automatic synthesis of extended burst-mode circuits Part 2 (Automatic synthesis)", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18 no. 2, February, 1999, pp. 118 - 312.
        13. Biblink
    4. Synthesis, testing, verification, dealing with problems
      1. S. Banerjee, New techniques for synthesis and testing of asynchronous circuits, PhD Thesis, University o f Massachusetts Amherst, Dept. of Electrical and Computer Engineering, 1995. Biblink
      2. David L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, The MIT Press, Cambridge, Massachusetts, 1989. Biblink
      3. Ian Gibson and Chris Amies, "Practical concurrent ASIC and system design and verification", Proceedings of the European Design and Test Conference, 1997, pp 532 - 536. Biblink
      4. Indradeep Ghosh and Niraj K. Jha, "High-level test synthesis: a survey", Integration: the VLSI journal, vol 26, 1998, pp 79 - 99.
      5. David A. Kearney, Performance Evaluation of Asynchronous Circuits, PhD Thesis, Space Centre for Satellite Navigation, Queensland University of Technology, 1998. Biblink
      6. Steven M. Nowick, Niraj K. Jha and Fu-Chiung Cheng, "Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16 no. 12, December, 1997, pp. 1514 - 1521. Biblink
      7. Rik van de Wiel, "High-level test evaluation of asynchronous circuits", Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, May 1995, pp 63 - 71. Biblink
    5. More general information
      1. Karl M. Fant and Scott A Brandt, "NULL convention logic" http://www.theseus.com/Downloads/NCLpaper.pdf, [online 17th November, 1998]. Biblink
      2. Karl M. Fant and Richard Stephani, Ross Smith and Ryan Jorgenson, "The orphan in 2 value NULL convention logic" http://www.theseus.com/Downloads/Orphan.pdf, [online 17th November, 1998]. Biblink
      3. Karl M. Fant, "A critical review of the notion of the algorithm in computer science" http://www.theseus.com/Downloads/Algorithm.pdf, [online 17th November, 1998]. Biblink
      4. Karl M. Fant and Ernest E. Hollis, "Clockless logic program" http://www.theseus.com/Downloads/PIMtg.pdf, [online 17th November, 1998]. Biblink
      5. S. B. Furber, "The return of asynchronous logic", http://www.cs.man.ac.uk/amulet/async/asyn_desc.html [online 25th June, 1998]. Biblink
      6. Luis A. Plana and Steven M. Nowick, "Concurrency-oriented optimization for low-power asynchronous systems", Proceedings of ISLPED, 1996, pp 151 - 156. Biblink
      7. Ching-Yi Wang, Dave Parker, Ryan Jorgenson and Karl M. Fant, "Technology independent design using NULL convention logic" http://www.theseus.com/Downloads/TechInd.pdf, [online 17th November, 1998]. Biblink
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    Created 22nd February 1999
    Last modified 15th April 1999