Jay Yantchev
Authored and Co-authored Research Publications
`Space Efficient Reachability Analysis Through Use of Pseudo Root States',
Third International Workshop on Tools and Algorithms for the Construction
and Analysis of Systems TACAS'97, Twente, Netherlands, April 1997.
`ARC --- A Verification Tool for Concurrent Systems', to appear in
Proc. of Australasian Conference on Parallel and Real-time Systems
PART'96, 1996.
`A Timed Analysis Technique for Single Processor Real-Time
Systems', to appear in Proc. of Australasian Conference on Parallel
and Real-time Systems PART'96, 1996.
`Predicting Real-Time Delay Bounds in Non-Rate Controlled FIFO
Networks', to appear in Proc. of Australasian Conference on
Parallel and Real-time Systems PART'96, 1996.
`Asynchronous Arbitration Circuits', IEEE Trans. on VLSI, Sep 1996.
`ARC - A Tool for Efficient Refinement and Equivalence Checking for
CSP' IEEE 2nd Int. Conf. on Algorithms and Architectures
for Parallel Processing ICA3PP'96, 1996.
`Efficient Refinement Checking for CSP using OBDD's' , Proc PART'95, Perth, Australia, Sep 1995.
`Asynchronous Arbitration Circuits,' to appear in IEEE Trans on VLSI, 1995.
`Low Latency Asynchronous FIFO Buffers,' Proc 2$^{nd $ Working Conference, Asynchronous Design Methodologies, IEEE Comp Sc Press, May 95.
`Fault-tolerant Real-time Communications with Reduced Resource Overhead,' Proc ACSC'95, Adelaide, January 95.
`Performance Evaluation of Fault-tolerant Routing Protocols for Real-Time Channels,' Proc Part'94, Melbourne, July 94, pp 305-312.
`Implementation of a Switching Device as a Delay-Insensitive Circuit,' Proc SIS'93 (Systems Integration Symposium'93), Seattle, WA, March 1993.
`High Level Design of an Asynchronous Packet Router,' Proc Workshop on Designing Correct Circuits, Lyngby, Denmark, January 1992.
`The MP1 Communications Processor,' Proc TRANSPUTING'91, Sunnyvale, CAL, USA, April 1991.
`Communication Abstraction and Refinement,' Proc PARLE'91, Eindhoven, NL, Lecture Notes in Comp Science, June 1991.
`Communication Refinement,' Proc 6$^{th $ Distr. Mem. Comp. Conf., Beaverton, OR, USA, IEEE Comp Sc Press, April 1991.
`Developing Powerful Communication Mechanisms from Simple and Efficient Packet Routing,' Proc. 5$^{th $ Distr. Mem. Comp. Conf. (DMCC'5), Charleston, USA, IEEE Comp Sc Press, May 1990.
`High Performance Communications in Processor Networks,' Proc. 16$^{th $ Annual Int. Symp. on Comp. Arch. (ISCA'16), Jerusalem, Israel, IEEE Comp Sc Press, 1989.
`High Performance Packet Routing Based on Systolic Arrays,' Proc. 3\(^{rd \) Intern Conf on Systolic Arrays, Killarney, Ireland, 1989.
`Adaptive, Low Latency, Deadlock-free Packet Routing for Processor Networks,' IEE Proc. E, May 1989.
`Programming With Active Data,' Proc PARCELLA'88, Berlin, 1988.
Thank you for visiting our site. For more information or if you have comments, contact
www@cs.adelaide.edu.au.